1. Field of Invention
Embodiments of the invention relate in general to a data transfer protocol. More specifically, the embodiments of the invention relate to methods and systems defining rules for the transmission of data, and synchronization and alignment of a receiver and a transmitter.
2. Description of the Background Art
Transmission of data across the backplane of a high-speed interface, e.g., 6.25 Gbps on a Serializer/Deserializer (SERDES), involves transfer of bit patterns in the form of packets (henceforth referred to as ‘payload’). The SERDES has a Decision Feedback Equalizer (DFE) circuit at the receiver. The DFE circuits maintain signal integrity and reduce bit error rates. However, the presence of extended idle bit patterns, such as continuous 0s or 1s, and intra packet gaps (IPGs) on a bus results in impairment in clock recovery and disturbances in DFE adaptation. A conventional protocol cannot avoid the extended idle bit patterns on the bus. In order to avoid these extended idle bit patterns, a protocol should define mechanisms for scrambling the payload at the interface of the transmitter. Scrambling is also necessary to avoid “intersymbol interferences.” An intersymbol interference is the distortion in the temporal spreading of the received signal. This distortion results in the overlap of the individual pulse of the signal, to the extent that the receiver cannot distinguish between changes of state, i.e., individual signal elements. Therefore, intersymbol interference compromises the integrity of the received payload. Further, if erroneous patterns are introduced after scrambling, descrambling the payload becomes difficult. The protocol should enable easier and faster recovery of the error, so that it is not propagated from one corrupted payload to subsequent payloads. Moreover, the mechanisms for scrambling payloads should be compatible with any coding scheme, without compromising the alignment scheme of the payload. Furthermore, the protocol should allow the extended idle bit patterns and intra packet special patterns to be sent within a packet.
During the unavailability of bandwidth in an Integrated Circuit such as an Application Specific Integrated Circuit (ASIC), the protocol communicates with the receiver and the transmitter to stall the transmission of packets. The protocol performs dynamic updating of the state information pertaining to the payload, thereby ensuring protocol active hardware clock recovery. Active hardware clock recovery results in improved data integrity and reduced bit error rates. Furthermore, the protocol ensures a higher level of control information for synchronous data transfer.
Existing protocols such as the Ethernet Protocol and the Cisco Protocol do not support the introduction of extended idle bit patterns and IPG during transmission of the payload. Moreover, none of the existing protocols avoid transmission of extended bit patterns when there is no traffic on the bus. These protocols do not also enable dynamic, easier and faster error recovery during transmission of the payload.
One of the existing algorithms for scrambling the payload randomizes the payload, based on the output bit that precedes it by N-bit positions. However, in the event of a transmission error, multiple errors may be produced in the descrambled data. The transmission error also propagates across frames.
Another scrambling algorithm defines a mechanism for sending the scrambling state of the transmitter through state synchronization messages. These messages are minimal size packets containing the state. However, these packets consume additional bandwidth and add an Inter Packet Group (IPG) overhead to packet transmission interfaces. Moreover, if there is a corruption in the state, it results in improper descrambling of the packets, which can be corrected only when the next message arrives.